History of binning a picture

Dear followers,

After a very long time, we finally managed to solve a simple problem, perform an on-live 4×4 binning to the pictures taken from the camera. This process is quite simple, we just need to take the pixels, make the columns binning by summing up each 4 of them and storing them into a FIFO queue (First Input First Output). Then, when the next line of pixels arrives, it is just to add them as before and add to them the previous 4 and store them again. After 4 times we have a full line make of 4×4 binned pixels. Then, it is just to save into our memory and later one retrieve the picture for plotting on Matlab.

Okay, once you get the concept, it is easy, isn’t it? However I was fighting a problem, the pictures were always wrong, the pixels shifted and strange values where in all of them. I checked the algorithm hundred of times, I discussed with other people about it in order to find the error, I tested it in different ways, and it was okay but some small issues. However it didn’t work, it was frustrating! Indeed, time was running and it wasn’t working yet.

Fortunately, few days ago, during a long simulation on ModelSim (a special software for checking the VHDL firmware without loading it into a device) shows something unusual. At one point, a COST component, generated by the tool that I was using for designing the firmware got an unexpected value. That gave me the key! This COST component was the FIFO, the same in which I was saving the values before sending into the memory. It wasn’t behaving in a normal mode. After that, I decided to make some modifications on that component, which shall be said, has been used successfully in different projects. The point is that we have a lot of free space in our FPGA but a small amount of RAM memory, which is used to build up the FIFO. For this reason I decided to use FIFO sizes different from a power of 2 (in digital electronics, that is magic). That strange manipulation is possible and the tool says that it is supported, however, after changing the size values to a power of 2, by wasting some RAM on it, the binning got life! The problem was solved!

Now, we have to keep working and take the next steps, we already have lost a lot of time with this bug, but now we know that this bug exists, and we can take care about it. However, and even after the fact that now the binning it’s working just by changing in there, I would like to double-check that the error is in there and if after that we think so, report it for the sake of all possible engineers which are dealing or will deal with the same problem.

And as a prof of that it works, here is the first picture taken with the binning fully operative!


Okay, it’s not the best picture ever, National Geographic won’t use it but remember, we will use this camera for tracking a powerful light, not for taking team pictures! or maybe…..

Story on Flight Dynamics Continuing

Up to last post, we had considered cases with drag with wind and not, and varying ejection angles. And all the simulations were based on the symmetry of FFUs. However, the more actual situation is that I22 does not equal I11. Therefore, in the past days, we took into account the varying I22/I11 ratio.

16 17


Fig.16 illustrates the changes of look angles with I22/I11 from 0.5 to 1.8. As I22/I11 increases, both the absolute values of maximum and minimum of look angles gradually grow till the ratio of 1.6, afterwards, these values rise fast. The changes are not larger than 1 degree, compared the maximum and minimum value of look angles Fig.16 with the ones in Fig.15 until I22/I11=1.6. Neverthless, when I22/I11 reaches 1.8, the maximum and minimum of look angles increases several degrees. As a consequence, over the interval of I22/I11 between 0.5 and 1.8, the maximum and minimum of look anlges are 5.27 deg and -10.76 deg, respectively, which are obtained when I22/I11 is 1.8.

Fig.a shows that look angles vary as ejection angles change when I22/I11 is held.
In Fig.a, star and circle represent the maximum and minimum of look angles, respectively. Red and black stand for look angles when I22/I11 equals 1.8 and 0.5, respectively. The maxima of look angles grow slowly, in contrast, the minima of look angles reduce gradually, as ejection angles become larger.

Okay, right now we have known the situation with asymmetrical geometry. What shall we do next? Next, we are going to consider the case when there is drag torque applied on FFUs. Let us wait for the new results.


Bending and cutting

With our fearless team leader exploring the wonders of the two biggest countries in the world (wrt area) and our outreach wizz showing around Stockholm to old friends, the responsibility of bending in cutting landed on my shoulders. And so since Monday I have made countless trips from the library (4th floor) to the workshop (deep deep under) and be, amazed, this is all I came up with. It doesn’t look like much but a lot of work and frustration went into those little things, half of which are not even in their final state.

The manufacturing phase has started already, at least according to the project plan, so what my intention with these baffles and straps was was to get accustomed to the workshop and the tools for when the more complicated parts will need to be manufactured. In both FFUs we have a couple of parts, like stepper motors, IR optical tubes and sensors, a camera lens and a few batteries, which need to be strapped into their respective positions. You can see below what my amazing bending skills produced.

2013-10-23 18.24.00

Straps. Various shapes and sizes (a lot more of them are in storage)

As for the baffles, they will prevent any stray light, that finds its way into the RxSU, from reaching the optical sensors. Cutting an aluminum 0.5 mm thick sheet with a cutter and a metal shears is not an easy task, but by the end I was surprised to see that, within a fairly reasonable margin of error, the part looked the same as it did in the CAD.

2013-10-23 18.23.36

One of the baffles that will make light behave!

2013-10-23 18.23.05

A close-up view of the baffle.

This is what keep me busy the past three days and hopefully by the end of the week we will start working on more serious parts. Nonetheless, it has been fun cutting and bending, but for the next time I’m definitely getting some help from one or both of these guys:

bender lasercutvision

Hello ISAAC readers!

I am a new member of the ISAAC project and for me it’s very exciting to work on such a great experiment. I was very lucky to to be inside this project. Three other friends and I work on the electronics part until Christmas.


We started with studying papers, writing project plan and the risk analysis which were the most important documents that we had to submit to our teacher in the project management course about the ISAAC project. Then defining and clarifying the interfaces of the PCBs were done.

Last week we started to be familiar with Mentor Graphic for printed circuit board (PCB) designing. Nikolay is our supervisor and he showed us how to use the tool. Using this tool is a little tricky. I already worked with Eagle, a free tool for PCB design; you can start with it if you are a beginner like me :). But it seems that Mentor Graphic is more complete than the free tools and already used in this project. Jorge and I are designing the Schematic and layout for the top power PCB at the moment. The schematic is in progress and the layout will be done after finishing the schematic.

You must know many details like voltage and minimum and maximum current about the devices that you produce power for. Information about the devices can be found in the datasheets. But Jorge helps a lot, a helpful and smiley guy that has a lot of experience and information.



Schematics and Board Layout

The whole electronics team has been working on the schematics and the board layouts. we are optimistic on that front. For those of you, who would like to know a bit more, I’ll briefly describe how we design a PCB (Printer circuit board) and why I like it.

First step of course is to determine the electronics components we are going to use. Then we create schematics, putting in all the necessary components and connecting them with each other, something like this: 



Schematics contains some big components and quite a lot of small components. Then the components should be connected. This could take a long time, especially if you have a component with for example 484 pins. But that’s the boring part. After the schematics is completed comes the best part: board layout.

Now we use images of real components to create the PCB itself. If you liked puzzles in your childhood, you would love to design PCBs. Just look at this:


It’s just the start of the design, but it show the idea. The green line represent connections that you have to create and the other color lines are those that are already created. The same color lines cannot cross each other. There are more rules, but these are the basic. This is just the start of the design, but it feels satisfying. Do you want to try?


The best thing (or the worst, it depends) is that computers bad at these designs, at least the one we are able to use. So people are left to design these pieces of art.

Running out of battery

Or at least that is the feeling in part of the electrical team this week.

The electrical team is currently formed by 6 people, Kevin, who spends his time in playing with our infra-red system. Georgi, who has been including an small component into the system libraries for using it in our PCBs. Babak, Ruslan, Jiazuo and me, Jorge, all we have been spending part of the last week and what is gone of this, which isn’t still over, fighting for 5 minutes more of sleeping time. And maybe you are asking yourself, “why is that?” (others just are thinking that we are lazy…). The reason of this is really simple, all we are in the same master programme, and unless one course, we have the same this period, which can be said, is the harder one in academic load in our master with around 25 credits instead of the usually 15. The point is that this week we have had to submit two different assignments and still tomorrow we have to submit another two more, and just to make a whole day, a presentation of one of those assignments. So, with 4 assignments in 3 days, and having access to start some of them less than one week ago, sleep time has become a valuable good for us….

However, if you have been following the REXUS project, you may be noticing that something is missing, and you are right!, Murphy is with us! Yesterday we submitted our SED v3.1! In this one we addressed several comments mainly in the formatting and we expanded our explanations in some chapters since ISAAC never stops! Fortunately, we have a really good team which supported us with the modifications and also addressing some of our supervisor comments. Thanks to their help, it can be said that we ow them at least 1 or 2 sleeping hours!

Thank you guys!